
`include "common_header.verilog"

//  *************************************************************************
//   File : top_xgxs_tx.vh
//  *************************************************************************
//   This program is controlled by a written license agreement.
//   Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2005 Morethanip GmbH
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: top_xgxs_tx.v,v 1.3 2011/08/31 13:10:45 dk Exp $ 
//  Author : Muhammad Anisur Rahman
//  *************************************************************************
//   Description:
// 
//   10 Gigabit Ethernet XGXS PCS Top-Level
// 
//  *************************************************************************

module top_xgxs_tx (

   reset_xgmii_txclk,
   xgmii_txclk,
`ifdef USE_CLK_ENA
   xgmii_txclk_ena,
`endif   
   xgmii_txd,
   xgmii_txc,
   sd0_tx,
   sd1_tx,
   sd2_tx,
   sd3_tx
`ifdef MTIPXGXS_EEE_ENA
   ,
   sw_reset,
   lpi_tick,
   tx_mode_quiet,
   tx_lpi_active
`endif   
   );

input   reset_xgmii_txclk;      //  Asynchronous Reset - xgmii_txclk Domain       
input   xgmii_txclk;            //  Transmit Clock
`ifdef USE_CLK_ENA
   input xgmii_txclk_ena;
`endif
input   [63:0] xgmii_txd;       //  Transmit Data
input   [7:0] xgmii_txc;        //  Transmit Control
output  [19:0] sd0_tx;          //  SERDES Lane 0
output  [19:0] sd1_tx;          //  SERDES Lane 1
output  [19:0] sd2_tx;          //  SERDES Lane 2
output  [19:0] sd3_tx;          //  SERDES Lane 3
`ifdef MTIPXGXS_EEE_ENA
input   sw_reset;               //  software driven sync reset
input   lpi_tick;               //  Timer Tick for all LPI timers
output  tx_mode_quiet;          //  tx_mode (0 - DATA, 1 - QUIET)
output  tx_lpi_active;          //  1 - the TX is in the Low Power State, 0 - in the Normal State

wire    tx_mode_quiet; 
wire    tx_lpi_active; 
`endif

wire    [19:0] sd0_tx; 
wire    [19:0] sd1_tx; 
wire    [19:0] sd2_tx; 
wire    [19:0] sd3_tx; 

wire    [15:0] din0;            //  Parallel byte of incoming data - Lane 0
wire    [1:0] kin0;             //  Special caracter request - Lane 0
wire    [15:0] din1;            //  Parallel byte of incoming data - Lane 1
wire    [1:0] kin1;             //  Special caracter request - Lane 1
wire    [15:0] din2;            //  Parallel byte of incoming data - Lane 2
wire    [1:0] kin2;             //  Special caracter request - Lane 2
wire    [15:0] din3;            //  Parallel byte of incoming data - Lane 3
wire    [1:0] kin3;             //  Special caracter request - Lane 3  	

xgxs_tx_cntl U_TX_CNTL (

          .reset(reset_xgmii_txclk),
          .clk(xgmii_txclk),
        `ifdef USE_CLK_ENA
           .clk_ena(xgmii_txclk_ena),
        `endif
          .txd(xgmii_txd),
          .txc(xgmii_txc),
          .din0(din0),
          .kin0(kin0),
          .din1(din1),
          .kin1(kin1),
          .din2(din2),
          .kin2(kin2),
          .din3(din3),
          .kin3(kin3)
        `ifdef MTIPXGXS_EEE_ENA
          ,
          .sw_reset(sw_reset),
          .lpi_tick(lpi_tick),
          .tx_mode_quiet(tx_mode_quiet),
          .tx_lpi_active(tx_lpi_active)
        `endif   
          );

top_enc8b10b U_ENC3 (

          .din(din3),
          .kin(kin3),
          .dout(sd3_tx),
          .clk(xgmii_txclk),
        `ifdef USE_CLK_ENA
           .clk_ena(xgmii_txclk_ena),
        `endif          
          .rst(reset_xgmii_txclk));

top_enc8b10b U_ENC2 (

          .din(din2),
          .kin(kin2),
          .dout(sd2_tx),
          .clk(xgmii_txclk),
        `ifdef USE_CLK_ENA
           .clk_ena(xgmii_txclk_ena),
        `endif
          .rst(reset_xgmii_txclk));

top_enc8b10b U_ENC1 (

          .din(din1),
          .kin(kin1),
          .dout(sd1_tx),
          .clk(xgmii_txclk),
        `ifdef USE_CLK_ENA
           .clk_ena(xgmii_txclk_ena),
        `endif
          .rst(reset_xgmii_txclk));

top_enc8b10b U_ENC0 (

          .din(din0),
          .kin(kin0),
          .dout(sd0_tx),
          .clk(xgmii_txclk),
        `ifdef USE_CLK_ENA
           .clk_ena(xgmii_txclk_ena),
        `endif
          .rst(reset_xgmii_txclk));

endmodule // module top_xgxs_tx